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ltc2656 1 2656fa block diagram features applications description octal 16-/12-bit rail-to-rail dacs with 10ppm/c max reference n mobile communications n process control and industrial automation n instrumentation n automatic test equipment n automotive n precision 10ppm/c max reference n maximum inl error: 4lsb at 16 bits n guaranteed monotonic over temperature n selectable internal or external reference n 2.7v to 5.5v supply range (ltc2656-l) n integrated reference buffers n ultralow crosstalk between dacs(<1nv?s) n power-on-reset to zero-scale/mid-scale n asynchronous ldac update pin n tiny 20-lead 4mm 5mm qfn and 20-lead thermally enhanced tssop packages the ltc ? 2656 is a family of octal 16-/12-bit rail-to-rail dacs with a precision integrated reference. the dacs have built-in high performance, rail-to-rail, output buffers and are guaranteed monotonic. the ltc2656-l has a full-scale output of 2.5v with the integrated 10ppm/c reference and operates from a single 2.7v to 5.5v supply. the ltc2656-h has a full-scale output of 4.096v with the integrated refer - ence and operates from a 4.5v to 5.5v supply. each dac can also operate with an external reference, which sets the dac full-scale output to two times the external reference voltage. these dacs communicate via a spi/microwire ? com - patible 4-wire serial interface which operates at clock rates up to 50mhz. the ltc2656 incorporates a power-on reset circuit that is controlled by the porsel pin. if porsel is tied to gnd the dacs reset to zero-scale. if porsel is tied to v cc , the dacs reset to mid-scale. register register internal reference register register register register register register register register register register register register register register decode control logic power-on reset 32-bit shift register refcomp refin/out v cc gnd dac a ref ref ref ref ref ref ref ref dac h v outh dac g v outg dac f v outf dac e v oute porsel sdo sdi 2656 ta01a clr reflo v outa dac b v outb dac c v outc dac d v outd sck ldac cs/ld code 128 inl (lsb) 0 1 2 65535 2656 ta01b ?1 ?2 ?4 16384 32768 49152 ?3 4 3 dac a dac b dac c dac d dac e dac f dac g dac h inl vs code l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5396245, 6891433.
ltc2656 2 2656fa absolute maximum ratings (notes 1, 2) fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 reflo v outa v outb refcomp v outc v outd refin/out ldac cs/ld sck gnd v cc v outh v outg v outf v oute porsel clr sdo sdi 21 t jmax = 150c, ja = 38c/w, jc = 10c/w exposed pad (pin 21) is gnd, must be soldered to pcb 20 19 18 17 7 8 top view 21 ufd package 20-lead (4mm 5mm) plastic qfn 9 10 6 5 4 3 2 1 11 12 13 14 15 16 v outb refcomp v outc v outd refin/out ldac v outh v outg v outf v oute porsel clr v outa reflo gnd v cc cs/ld sck sdi sdo t jmax = 150c, ja = 43c/w exposed pad (pin 21) is gnd, must be soldered to pcb pin configuration supply voltage (v cc ) ................................... C0.3v to 6v cs /ld, sck, sdi, ldac , clr , reflo .......... C0.3v to 6v v outa to v outh ................. C0.3v to min(v cc + 0.3v, 6v) refin/out, refcomp ...... C0.3v to min(v cc + 0.3v, 6v) porsel, sdo ................... C0.3v to min(v cc + 0.3v, 6v) operating temperature range ltc2656c ................................................ 0c to 70c ltc2656i .............................................. C40c to 85c maximum junction temperature ........................... 150c storage temperature range ....................... C65 to 150c lead temperature (soldering, 10 sec) fe package ....................................................... 300c
ltc2656 3 2656fa product selector guide ltc2656 b c ufd -l 16 #tr pbf lead free designator pbf = lead free tape and reel tr = tape and reel resolution 16 = 16-bit 12 = 12-bit full-scale voltage, internal reference mode l = 2.5v h = 4.096v package type ufd = 20-lead (4mm 5mm) plastic qfn fe = 20-lead thermally enhanced tssop temperature grade c = commercial temperature range (0c to 70c) i = industrial temperature range (C40c to 85c) electrical grade (optional) b = 4lsb maximum inl (16-bit) c = 12lsb maximum inl (16-bit) product part number consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc2656 4 2656fa order information lead free finish tape and reel part marking* package description temperature range maximum inl ltc2656bcfe-l16#pbf ltc2656bife-l16#pbf ltc2656bcfe-l16#trpbf ltc2656bife-l16#trpbf ltc2656fe-l16 ltc2656fe-l16 20-lead thermally enhanced tssop 20-lead thermally enhanced tssop 0c to 70c C40c to 85c 4 4 ltc2656bcufd-l16#pbf ltc2656biufd-l16#pbf ltc2656bcufd-l16#trpbf ltc2656biufd-l16#trpbf 56l16 56l16 20-lead (4mm 5mm) plastic qfn 20-lead (4mm 5mm) plastic qfn 0c to 70c C40c to 85c 4 4 ltc2656bcfe-h16#pbf ltc2656bife-h16#pbf ltc2656bcfe-h16#trpbf ltc2656bife-h16#trpbf ltc2656fe-h16 ltc2656fe-h16 20-lead thermally enhanced tssop 20-lead thermally enhanced tssop 0c to 70c C40c to 85c 4 4 ltc2656bcufd-h16#pbf ltc2656biufd-h16#pbf ltc2656bcufd-h16#trpbf ltc2656biufd-h16#trpbf 56h16 56h16 20-lead (4mm 5mm) plastic qfn 20-lead (4mm 5mm) plastic qfn 0c to 70c C40c to 85c 4 4 ltc2656ccfe-l16#pbf ltc2656cife-l16#pbf ltc2656ccfe-l16#trpbf ltc2656cife-l16#trpbf ltc2656cfe-l16 ltc2656cfe-l16 20-lead thermally enhanced tssop 20-lead thermally enhanced tssop 0c to 70c C40c to 85c 12 12 ltc2656ccufd-l16#pbf ltc2656ciufd-l16#pbf ltc2656ccufd-l16#trpbf ltc2656ciufd-l16#trpbf 6cl16 6cl16 20-lead (4mm 5mm) plastic qfn 20-lead (4mm 5mm) plastic qfn 0c to 70c C40c to 85c 12 12 ltc2656cfe-l12#pbf ltc2656ife-l12#pbf ltc2656cfe-l12#trpbf ltc2656ife-l12#trpbf ltc2656fe-l12 ltc2656fe-l12 20-lead thermally enhanced tssop 20-lead thermally enhanced tssop 0c to 70c C40c to 85c 1 1 ltc2656cufd-l12#pbf ltc2656iufd-l12#pbf ltc2656cufd-l12#trpbf ltc2656iufd-l12#trpbf 56l12 56l12 20-lead (4mm 5mm) plastic qfn 20-lead (4mm 5mm) plastic qfn 0c to 70c C40c to 85c 1 1 ltc2656cfe-h12#pbf ltc2656ife-h12#pbf ltc2656cfe-h12#trpbf ltc2656ife-h12#trpbf ltc2656fe-h12 ltc2656fe-h12 20-lead thermally enhanced tssop 20-lead thermally enhanced tssop 0c to 70c C40c to 85c 1 1 ltc2656cufd-h12#pbf ltc2656iufd-h12#pbf ltc2656cufd-h12#trpbf ltc2656iufd-h12#trpbf 56h12 56h12 20-lead (4mm 5mm) plastic qfn 20-lead (4mm 5mm) plastic qfn 0c to 70c C40c to 85c 1 1 consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult ltc marketing for information on non-standard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ltc2656 5 2656fa electrical characteristics symbol parameter conditions min typ max units v out dac output span internal reference external reference = v extref 0 to 2.5 0 to 2 ? v extref v v psr power supply rejection v cc 10% C80 db r out dc output impedance v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.15 v cc = 3v 10%, internal reference, mid-scale, C7.5ma i out 7.5ma l 0.04 0.15 dc crosstalk (note 5) due to full-scale output change due to load current change due to powering down (per channel) 1.5 2 1 v v/ma v i sc short-circuit output current (note 6) v cc = 5.5v, v extref = 2.75v code: zero-scale, forcing output to v cc code: full-scale, forcing output to gnd l l 20 20 65 65 ma ma v cc = 2.7v, v extref = 1.35v code: zero-scale, forcing output to v cc code: full-scale, forcing output to gnd l l 10 10 40 40 ma ma reference reference output voltage 1.248 1.25 1.252 v reference temperature coefficient c-grade (note 7) i-grade (note 7) 2 2 10 ppm/c ppm/c reference line regulation v cc 10% C80 db reference short-circuit current v cc = 5.5v, forcing output to gnd l 3 5 ma refcomp pin short-circuit current v cc = 5.5v, forcing output to gnd l 60 200 a reference load regulation v cc = 3v 10% or 5v 10%, i out = 100a sourcing 40 mv/ma reference output voltage noise density c refcomp = c refin/out = 0.1f at f = 1khz 30 nv/ hz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. ltc2656b-l16/ltc2656c-l16/ltc2656-l12 (internal reference = 1.25v) symbol parameter conditions ltc2656-l12 ltc2656b-l16/ ltc2656c-l16 units min typ max min typ max dc performance resolution l 12 16 bits monotonicity (note 3) l 12 16 bits dnl differential nonlinearity (note 3) l 0.1 0.5 0.3 1 lsb inl integral nonlinearity (note 3) ltc2656b-l16: v cc = 5.5v, v ref = 2.5v ltc2656c-l16: v cc = 5.5v, v ref = 2.5v l l 0.5 1 2 6 4 12 lsb lsb load regulation v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.125 0.6 2 lsb/ma v cc = 3v 10%, internal reference, mid-scale, C7.5ma i out 7.5ma l 0.06 0.25 1 4 lsb/ma zse zero-scale error l 1 3 1 3 mv v os offset error v ref = 1.25v (note 4) l 1 2 1 2 mv v os temperature coefficient 2 2 v/c ge gain error l 0.02 0.1 0.02 0.1 %fsr gain temperature coefficient 1 1 ppm/c
ltc2656 6 2656fa symbol parameter conditions min typ max units reference input range external reference mode (note 13) l 0.5 v cc /2 v reference input current l 0.001 1 a reference input capacitance (note 9) l 40 pf power supply v cc positive supply voltage for specified performance l 2.7 5.5 v i cc supply current (note 8) v cc = 5v, internal reference on v cc = 5v, internal reference off v cc = 3v, internal reference on v cc = 3v, internal reference off l l l l 3.1 2.7 3.0 2.6 4.25 3.7 3.8 3.2 ma ma ma ma i shdn supply current in shutdown mode (note 8) v cc = 5v l 3 a digital i/o v ih digital input high voltage v cc = 3.6v to 5.5v v cc = 2.7v to 3.6v l l 2.4 2.0 v v v il digital input low voltage v cc = 4.5v to 5.5v v cc = 2.7v to 4.5v l l 0.8 0.6 v v v oh digital output high voltage load current = C100a l v cc C 0.4 v v ol digital output low voltage load current = 100a l 0.4 v i lk digital input leakage v in = gnd to v cc l 1 a c in digital input capacitance (note 9) l 8 pf ac performance t s settling time (note 10) 0.024% (1lsb at 12 bits) 0.0015% (1lsb at 16 bits) 4.2 8.9 s s settling time for 1lsb step 0.024% (1lsb at 12 bits) 0.0015% (1lsb at 16 bits) 2.2 4.9 s s voltage output slew rate 1.8 v/s capacitive load driving 1000 pf glitch impulse (note 11) at mid-scale transition, v cc = 3v 3 nv?s dac-to-dac crosstalk (note 12) due to full-scale output change, c refcomp = c refout = no load 2 nv?s multiplying bandwidth 150 khz e n output voltage noise density at f = 1khz at f = 10khz 85 80 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, internal reference 0.1hz to 200khz, internal reference 8 600 v p-p v p-p electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 2.7v to 5.5v, v out unloaded unless otherwise specified. ltc2656b-l16/ltc2656c-l16/ltc2656-l12 (internal reference = 1.25v)
ltc2656 7 2656fa electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specified. ltc2656b-h16/ltc2656-h12 (internal reference = 2.048v) symbol parameter conditions ltc2656-h12 ltc2656b-h16 units min typ max min typ max dc performance resolution l 12 16 bits monotonicity (note 3) l 12 16 bits dnl differential nonlinearity (note 3) l 0.1 0.5 0.3 1 lsb inl integral nonlinearity (note 3) v cc = 5.5v, v ref = 2.5v l 0.5 1 2 4 lsb load regulation v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.125 0.6 2 lsb/ma zse zero-scale error l 1 3 1 3 mv v os offset error v ref = 2.048v (note 4) l 1 2 1 2 mv v os temperature coefficient 2 2 v/c ge gain error l 0.02 0.1 0.02 0.1 %fsr gain temperature coefficient 1 1 ppm/c symbol parameter conditions min typ max units v out dac output span internal reference external reference = v extref 0 to 4.096 0 to 2 ? v extref v v psr power supply rejection v cc 10% C80 db r out dc output impedance v cc = 5v 10%, internal reference, mid-scale, C15ma i out 15ma l 0.04 0.15 dc crosstalk (note 5) due to full-scale output change due to load current change due to powering down (per channel) 1.5 2 1 v v/ma v i sc short-circuit output current (note 6) v cc = 5.5v, v extref = 2.75v code: zero-scale, forcing output to v cc code: full-scale, forcing output to gnd l l 20 20 65 65 ma ma reference reference output voltage 2.044 2.048 2.052 v reference temperature coefficient c-grade (note 7) i-grade (note 7) 2 2 10 ppm/c ppm/c reference line regulation v cc 10% C80 db reference short-circuit current v cc = 5.5v, forcing output to gnd l 3 5 ma refcomp pin short-circuit current v cc = 5.5v, forcing output to gnd l 60 200 a reference load regulation v cc = 5v 10%, i out = 100a sourcing 40 mv/ma reference output voltage noise density c refcomp = c refin/out = 0.1f at f = 1khz 35 nv/ hz reference input range external reference mode (note 13) l 0.5 v cc /2 v reference input current l 0.001 1 a reference input capacitance (note 9) l 40 pf
ltc2656 8 2656fa symbol parameter conditions min typ max units power supply v cc positive supply voltage for specified performance l 4.5 5.5 v i cc supply current (note 8) v cc = 5v, internal reference on v cc = 5v, internal reference off l l 3.3 3.0 4.25 3.7 ma ma i shdn supply current in shutdown mode (note 8) v cc = 5v l 3 a digital i/o v ih digital input high voltage v cc = 4.5v to 5.5v l 2.4 v v il digital input low voltage v cc = 4.5v to 5.5v l 0.8 v v oh digital output high voltage load current = C100a l v cc C 0.4 v v ol digital output low voltage load current = 100a l 0.4 v i lk digital input leakage v in = gnd to v cc l 1 a c in digital input capacitance (note 9) l 8 pf ac performance t s settling time (note 10) 0.024% (1lsb at 12 bits) 0.0015% (1lsb at 16 bits) 4.6 7.9 s s settling time for 1lsb step 0.024% (1lsb at 12 bits) 0.0015% (1lsb at 16 bits) 2.0 3.8 s s voltage output slew rate 1.8 v/s capacitive load driving 1000 pf glitch impulse (note 11) at mid-scale transition, v cc = 5v 6 nv?s dac-to-dac crosstalk (note 12) due to full-scale output change, c refcomp = c refout = no load 3 nv?s multiplying bandwidth 150 khz e n output voltage noise density at f = 1khz at f = 10khz 85 80 nv/ hz nv/ hz output voltage noise 0.1hz to 10hz, internal reference 0.1hz to 200khz, internal reference 12 650 v p-p v p-p electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 4.5v to 5.5v, v out unloaded unless otherwise specified. ltc2656b-h16/ltc2656-h12 (internal reference = 2.048v)
ltc2656 9 2656fa electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltages are with respect to gnd. note 3: linearity and monotonicity are defined from code kl to code 2 n C 1, where n is the resolution and kl is the lower end code for which no output limiting occurs. for v ref = 2.5v and n = 16, kl = 128 and linearity is defined from code 128 to code 65535. for v ref = 2.5v and n = 12, kl = 8 and linearity is defined from code 8 to code 4,095. note 4: inferred from measurement at code 128 (ltc2656-16) or code 8 (ltc2656-12). note 5: dc crosstalk is measured with v cc = 5v and using internal reference with the measured dac at mid-scale. note 6: this ic includes current limiting that is intended to protect the device during momentary overload conditions. junction temperature can exceed the rated maximum during current limiting. continuous operation above the specified maximum operating junction temperature may impair device reliability. symbol parameter conditions min typ max units v cc = 2.7v to 5.5v t 1 sdi valid to sck setup l 4 ns t 2 sdi valid to sck hold l 4 ns t 3 sck high time l 9 ns t 4 sck low time l 9 ns t 5 cs /ld pulse width l 10 ns t 6 lsb sck high to cs /ld high l 7 ns t 7 cs /ld low to sck high l 7 ns t 8 sdo propagation delay from sck falling edge c load = 10pf v cc = 4.5v to 5.5v v cc = 2.7v to 4.5v l l 20 45 ns ns t 9 clr pulse width l 20 ns t 10 cs /ld high to sck positive edge l 7 ns t 12 ldac pulse width l 15 ns t 13 cs /ld high to ldac high or low transition l 200 ns sck frequency 50% duty cycle l 50 mhz the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. ltc2656b-l16/ltc2656c-l16/ltc2656-l12/ltc2656b-h16/ltc2656-h12 (see figure 1). note 7: temperature coefficient is calculated by dividing the maximum change in output voltage by the specified temperature range. note 8: digital inputs at 0v or v cc . note 9: guaranteed by design and not production tested. note 10: internal reference mode. dac is stepped 1/4 scale to 3/4 scale and 3/4 scale to 1/4 scale. load is 2k in parallel with 200pf to gnd. note 11: v cc = 5v, internal reference mode. dac is stepped 1lsb between half scale and half scale C 1lsb. load is 2k in parallel with 200pf to gnd. note 12: dac-to-dac crosstalk is the glitch that appears at the output of one dac due to a full-scale change at the output of another dac. it is measured with v cc = 5v and using internal reference, with the measured dac at mid-scale. note 13: gain error specification may be degraded for reference input voltages less than 1v. see gain error vs reference input voltage curve in the typical performance characteristics section.
ltc2656 10 2656fa typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature refout voltage vs temperature settling to 1lsb rising settling to 1lsb falling t a = 25c unless otherwise noted. code 128 inl (lsb) 0 1 2 65535 2656 g01 ?1 ?2 ?4 16384 32768 49152 ?3 4 v cc = 3v 3 code 128 dnl (lsb) 0 0.5 65535 2656 g02 ?0.5 ?1.0 16384 32768 49152 1.0 v cc = 3v temperature (c) ?50 inl (lsb) 0 1 2 110 2656 g03 ?1 ?2 ?4 ?10 30 70 ?30 130 10 50 90 ?3 4 3 inl (pos) v cc = 3v inl (neg) temperature (c) ?50 dnl (lsb) 0 0.5 110 2656 g04 ?0.5 ?1.0 ?10 30 70 ?30 130 10 50 90 1.0 dnl (pos) v cc = 3v dnl (neg) temperature (c) ?50 v ref (v) 1.251 1.250 1.249 1.248 1.247 1.252 ?10 30 50 130 2656 g05 ?30 10 70 90 110 1.253 v cc = 3v v out 100v/div cs/ld 3v/div 2s/div 2656 g06 1/4 scale to 3/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 200pf average of 2048 events 8.9s 2s/div 2656 g07 cs/ld 3v/div v out 100v/div 3/4 scale to 1/4 scale step v cc = 3v, v fs = 2.5v r l = 2k, c l = 200pf average of 2048 events 8.7s ltc2656-l16
ltc2656 11 2656fa integral nonlinearity (inl) differential nonlinearity (dnl) inl vs temperature dnl vs temperature refout voltage vs temperature settling to 1lsb rising settling to 1lsb falling ltc2656-h16 code 128 inl (lsb) 0 1 2 65535 2656 g08 ?1 ?2 ?4 16384 32768 49152 ?3 4 v cc = 5v 3 code 128 dnl (lsb) 0 0.5 65535 2656 g09 ?0.5 ?1.0 16384 32768 49152 1.0 v cc = 5v temperature (c) ?50 inl (lsb) 0 1 2 110 2656 g10 ?1 ?2 ?4 ?10 30 70 ?30 130 10 50 90 ?3 4 3 inl (pos) v cc = 5v inl (neg) temperature (c) ?50 dnl (lsb) 0 0.5 110 2656 g11 ?0.5 ?1.0 ?10 30 70 ?30 130 10 50 90 1.0 dnl (pos) v cc = 5v dnl (neg) temperature (c) ?50 v ref (v) 2.050 2.048 2.046 2.044 2.042 2.052 ?10 30 50 130 2656 g12 ?30 10 70 90 110 2.054 v cc = 5v v out 250v/div cs/ld 5v/div 2s/div 2656 g13 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.096v r l = 2k, c l = 200pf average of 2048 events 7.9s v out 250v/div cs/ld 5v/div 2s/div 2656 g14 6.1s 3/4 scale to 1/4 scale step v cc = 5v, v fs = 4.096v r l = 2k, c l = 200pf average of 2048 events typical performance characteristics t a = 25c unless otherwise noted.
ltc2656 12 2656fa integral nonlinearity (inl) differential nonlinearity (dnl) settling to 1lsb (12 bit) rising load regulation current limiting headroom at rails vs output current ltc2656-12 offset error vs temperature zero-scale error vs temperature gain error vs temperature ltc2656-16 code 8 inl (lsb) 0 0.5 4095 2656 g15 ?0.5 ?1.0 1024 2048 3072 1.0 v cc = 5v v ref = 2.048v code 8 dnl (lsb) 0 0.5 4095 2656 g16 ?0.5 ?1.0 1024 2048 3072 1.0 v cc = 5v v ref = 2.048v v out 1mv/div cs/ld 5v/div 2s/div 2656 g17 1/4 scale to 3/4 scale step v cc = 5v, v fs = 4.095v r l = 2k, c l = 200pf average of 2048 events 4.6s i out (ma) ?50 ?v out (mv) 2 6 10 30 2656 g18 ?4 0 4 8 ?2 ?6 ?8 ?10 ?30 ?40 ?10 ?20 10 20 40 0 50 v cc = 5v (ltc2656-h) v cc = 3v (ltc2656-l) internal ref. code = mid-scale i out (ma) ?50 ?v out (v) 0 0.10 0.20 30 2656 g19 ?0.10 ?0.05 0.05 0.15 ?0.15 ?0.20 ?30 ?40 ?10 ?20 10 20 40 0 50 v cc = 5v (ltc2656-h) v cc = 3v (ltc2656-l) internal ref. code = mid-scale i out (ma) 0 v out (v) 3.0 4.0 5.0 8 2656 g20 2.0 1.0 2.5 3.5 4.5 1.5 0.5 0 2 1 4 3 6 7 9 5 10 5v sourcing 5v sinking 3v sourcing (ltc2656-l) 3v sinking (ltc2656-l) temperature (c) ?50 offset error (mv) 0 0.25 0.50 110 3656 g21 ?0.25 ?0.50 ?1.00 ?10 30 70 ?30 130 10 50 90 ?0.75 1.00 0.75 temperature (c) ?50 0 zero-scale error (mv) 0.5 1.5 2.0 2.5 ?10 30 50 130 2656 g22 1.0 ?30 10 70 90 110 3.0 temperature (c) ?50 gain error (lsb) 0 16 32 110 2656 g23 ?16 ?32 ?64 ?10 30 70 ?30 130 10 50 90 ?48 64 48 typical performance characteristics t a = 25c unless otherwise noted.
ltc2656 13 2656fa offset error vs reference input gain error vs reference input i cc shutdown vs v cc supply current vs logic voltage hardware clr to mid-scale hardware clr to zero-scale ltc2656-16 multiplying bandwidth large-signal response mid-scale glitch impulse reference voltage (v) 0.5 offset error (mv) 0 0.5 1.0 2.5 2656 g24 ?0.5 ?1.0 ?2.0 1.0 1.5 2.0 ?1.5 2.0 1.5 v cc = 5.5v offset error of 8 channels reference voltage (v) 0.5 gain error (lsbs) 0 16 32 2.5 2656 g25 ?16 ?32 ?64 1.0 1.5 2.0 ?48 64 48 v cc = 5.5v gain error of 8 channels v cc (v) 2.5 0 i cc (na) 50 150 200 250 4.5 450 2656 g26 100 3.5 3.0 5.0 4.0 5.5 300 350 400 logic voltage (v) 0 i cc (ma) 3.2 3.6 4.0 4 2656 g27 2.8 2.4 2.0 1 2 3 5 sweep sck, sdi, cs/ld between 0v and v cc v cc = 5v (ltc2656-h) v cc = 3v (ltc2656-l) v out 1v/div clr 5v/div 2656 g28 1s/div v cc = 5v v ref = 2.048v code = full-scale v out 1v/div clr 5v/div 2656 g29 1s/div v cc = 5v v ref = 2.048v code = full-scale frequency (hz) 1k ?4 magnitude (db) ?2 0 2 4 10k 100k 1m 2656 g30 ?6 ?8 ?10 ?12 6 8 v cc = 5v v ref(dc) = 2v v ref(ac) = 0.2v p-p code = full-scale v out 1v/div 2656 g31 2.5s/div v cc = 5v v ref = 2.048v zero-scale to full-scale v out 5mv/div v out 5mv/div cs/ld 5v/div 2656 g32 2s/div v cc = 5v, 6nv?s typ (ltc2656-h16) v cc = 3v, 3nv?s typ (ltc2656-l16) typical performance characteristics t a = 25c unless otherwise noted.
ltc2656 14 2656fa dac-to-dac crosstalk (dynamic) power-on reset glitch power-on reset to mid-scale noise voltage vs frequency 0.1hz to 10hz voltage noise reference 0.1hz to 10hz voltage noise ltc2656 v out 2mv/div v out 2mv/div one dac switch 0-fs 2v/div 2656 g32 2s/div ltc2656-h16, v cc = 5v, 3nv?s typ c refcomp = c refout = no load ltc2656-h16, v cc = 5v, <1nv?s typ c refcomp = c refout = 0.1f 2656 g34 200s/div v cc 2v/div v out 10mv/div zero-scale 2656 g35 250s/div v cc 2v/div v out 1v/div ltc2656-h frequency (hz) 1 10 noise voltage (nv/hz) 200 400 600 800 100 1k 10k 100k 1m 2656 g36 0 1000 1200 ltc2656-h ltc2656-l v cc = 5v code = mid-scale internal ref c refcomp = c refout = 0.1f 5v/div 2656 g37 1 sec/div v cc = 5v, v fs = 2.5v code = mid-scale internal ref c refcomp = c refout = 0.1f 2v/div 2656 g38 1 sec/div v refout = 1.25v c refcomp = c refout = 0.1f typical performance characteristics t a = 25c unless otherwise noted.
ltc2656 15 2656fa pin functions reflo (pin 1/pin 19): reference low pin. the voltage at this pin sets the zero-scale voltage of all dacs. reflo should be tied to gnd. v outa to v outh (pins 2, 3, 5, 6, 15, 16, 17, 18/pins 20, 1, 3, 4, 13, 14, 15, 16): dac analog voltage out - puts. the output range is 0v to 2 times the voltage at the refin/out pin. refcomp (pin 4/pin 2): internal reference compensa - tion pin. for low noise and reference stability, tie a 0.1f capacitor to gnd. connect refcomp to gnd to allow the use of external reference at start-up. refin/out (pin 7/pin 5): this pin acts as the internal reference output in internal reference mode and acts as the reference input pin in external reference mode. when acting as an output, the nominal voltage at this pin is 1.25v for l options and 2.048v for h options. for low noise and reference stability tie a capacitor from this pin to gnd. this capacitor value must be c refcomp , where c refcomp is the capacitance tied to the refcomp pin. in external reference mode, the allowable reference input voltage range is 0.5v to v cc /2. ldac (pin 8/pin 6): asynchronous dac update pin. if cs /ld is high, a falling edge on ldac immediately updates the dac register with the contents of the input register (similar to a software update). if cs /ld is low when ldac goes low, the dac register is updated after cs /ld returns high. a low on the ldac pin powers up the dac outputs. all the software power-down commands are ignored if ldac is low when cs /ld goes high. cs /ld (pin 9/pin 7): serial interface chip select/load input. when cs /ld is low, sck is enabled for shifting data on sdi into the register. when cs /ld is taken high, sck is disabled and the specified command (see table 1) is executed. (tssop/qfn) sck (pin 10/pin 8): serial interface clock input. cmos and ttl compatible. sdi (pin 11/pin 9): serial interface data input. data is applied to sdi for transfer to the device at the rising edge of sck (pin 10). the ltc2656 accepts input word lengths of either 24 or 32 bits. sdo (pin 12/pin 10): serial interface data output. this pin is used for daisy-chain operation. the serial output of the shift register appears at the sdo pin. the data transferred to the device via the sdi pin is delayed 32 sck rising edges before being output at the next falling edge. this pin is continuously driven and does not go high impedance when cs /ld is taken active high. clr (pin 13/pin 11): asynchronous clear input. a logic low at this level-triggered input clears all registers and causes the dac voltage outputs to drop to 0v if the porsel pin is tied to gnd. if the porsel pin is tied to v cc , a logic low at clr sets all registers to mid-scale code and causes the dac voltage outputs to go to mid-scale. porsel (pin 14/pin 12): power-on reset select pin. if tied to gnd, the dac resets to zero-scale at power-up. if tied to v cc , the dac resets to mid-scale at power-up. v cc (pin 19/pin 17): supply voltage input. for -l op - tions, 2.7v v cc 5.5v and for -h options, 4.5v v cc 5.5v. gnd (pin 20/pin 18): ground. exposed pad (pin 21/pin 21): ground. must be soldered to pcb ground.
ltc2656 16 2656fa block diagram register register internal reference register register register register register register register register register register register register register register decode control logic power-on reset 32-bit shift register refcomp refin/out v cc gnd dac a ref ref ref ref ref ref ref ref dac h v outh dac g v outg dac f v outf dac e v oute porsel sdo sdi 2656 bd clr reflo v outa dac b v outb dac c v outc dac d v outd sck ldac cs/ld
ltc2656 17 2656fa timing diagrams sdi sdo cs/ld sck 2656 f01a t 2 t 8 t 10 t 5 t 7 t 6 t 1 ldac t 3 t 4 1 2 3 23 24 t 13 t 12 cs/ld 2656 f01b t 13 ldac figure 1a figure 1b
ltc2656 18 2656fa operation the ltc2656 is a family of octal voltage output dacs in 20-lead 4mm 5mm qfn and in 20-lead thermally en - hanced tssop packages. each dac can operate rail-to-rail in external reference mode, or with its full-scale voltage set by an integrated reference. four combinations of ac - curacy (16-bit and 12-bit), and full-scale voltage (2.5v or 4.096v) are available. the ltc2656 is controlled using a 4-wire spi/microwire compatible interface. power-on reset the ltc2656-l/ ltc2656-h clear the output to zero-scale if the porsel pin is tied to gnd, when power is first applied, making system initialization consistent and repeatable. for some applications, downstream circuits are active during dac power-up and may be sensitive to nonzero outputs from the dac during this time. the ltc2656 contains circuitry to reduce the power-on glitch. the analog outputs typically rise less than 10mv above zero-scale during power on if the power supply is ramped to 5v in 1ms or more. in general, the glitch amplitude decreases as the power supply ramp time is increased. see power-on reset glitch in the typical performance characteristics. alternatively, if the porsel pin is tied to v cc , the ltc2656 - l/ ltc2656-h sets the output to mid-scale when power is first applied. power supply sequencing and start-up for the ltc2656 family of parts, the internal reference is powered up at start-up by default. if an external reference is to be used, the refcomp pin must be hardwired to gnd. having refcomp hardwired to gnd at power up will cause the refin/out pin to become high impedance and will allow for the use of an external reference at start- up. however in this configuration, the internal reference will still be on even though it is disconnected from the refin/out pin and will draw supply current. in order to use external reference after power-up, the command select external reference (0111b) should be used to turn the internal reference off (see table 1.) the voltage at refin/out should be kept within the range C 0.3v refin/out v cc + 0.3v if the external reference is to be used (see absolute maximum ratings). particular care should be taken to observe these limits during power supply turn-on and turn-off sequences, when the voltage at v cc is in transition. transfer function the digital-to-analog transfer function is: v o u t ( i d e a l ) = k 2 n ? ? ? ? ? ? ? 2 ? v r e f C v r e f l o ( ) + v r e f l o where k is the decimal equivalent of the binary dac input code, n is the resolution of the dac, and v ref is the volt - age at the refin/out pin. the resulting dac output span is 0v to 2 ? v ref , as it is necessary to tie reflo to gnd. v ref is nominally 1.25v for ltc2656-l and 2.048v for ltc2656-h, in internal reference mode. table 1. command and address codes command* c3 c2 c1 c0 0 0 0 0 write to input register n 0 0 0 1 update (power up) dac register n 0 0 1 0 write to input register n, update (power up) all 0 0 1 1 write to and update (power up) n 0 1 0 0 power down n 0 1 0 1 power down chip (all dacs and reference) 0 1 1 0 select internal reference (power-up reference) 0 1 1 1 select external reference (power-down reference) 1 1 1 1 no operation address (n)* a3 a2 a1 a0 0 0 0 0 dac a 0 0 0 1 dac b 0 0 1 0 dac c 0 0 1 1 dac d 0 1 0 0 dac e 0 1 0 1 dac f 0 1 1 0 dac g 0 1 1 1 dac h 1 1 1 1 all dacs *command and address codes not shown are reserved and should not be used. serial interface the cs /ld input is level triggered. when this input is taken low, it acts as a chip-select signal, powering on the sdi and sck buffers and enabling the input shift register. data (sdi input) is transferred at the next 24 rising sck edges.
ltc2656 19 2656fa operation the 4-bit command, c3-c0, is loaded first; followed by the 4-bit dac address, a3-a0; and finally the 16-bit data word. for the ltc2656-16 the data word comprises the 16-bit input code, ordered msb-to-lsb. for the ltc2656-12 the data word comprises the 12-bit input code, ordered msb- to-lsb, followed by four dont care bits. data can only be transferred to the ltc2656 when the cs /ld signal is low. the rising edge of cs /ld ends the data transfer and causes the device to carry out the action specified in the 24-bit input word. the complete sequence is shown in figure 2a. the command (c3-c0) and address (a3-a0) assignments are shown in table 1. the first four commands in the table consist of write and update operations. a write operation loads a 16-bit data word from the 32-bit shift register into the input register of the selected dac, n. an update operation copies the data word from the input register to the dac register. once copied into the dac register, the data word becomes the active 16- or 12-bit input code, and is converted to an analog voltage at the dac output. the update operation also powers up the selected dac if it had been in power-down mode. the data path and registers are shown in the block diagram. while the minimum input word is 24 bits, it may option - ally be extended to 32 bits. to use the 32-bit word width, 8 dont-care bits must be transferred to the device first, followed by the 24-bit word as just described. figure 2b shows the 32-bit sequence. the 32-bit word is required for daisy-chain operation, and is also available to accommodate microprocessors that have a minimum word width of 16 bits (2 bytes). the 16-bit data word is ignored for all commands that do not include a write operation. daisy-chain operation the serial output of the shift register appears at the sdo pin. data transferred to the device from the sdi input is delayed 32 sck rising edges before being output at the next sck falling edge. the sdo pin is continuously driven and does not go high impedance when cs /ld is taken active high. the sdo output can be used to facilitate control of multiple serial devices from a single 3-wire serial port (i.e., sck, sdi and cs /ld). such a daisy-chain series is configured by connecting sdo of each upstream device to sdi of the next device in the chain. the shift registers of the devices are thus connected in series, effectively forming a single input shift register which extends through the entire chain. because of this, the devices can be addressed and controlled individually by simply concatenating their input words; the first instruction addresses the last device in the chain and so forth. the sck and cs /ld signals are common to all devices in the series. in use, cs /ld is first taken low. then the concatenated input data is transferred to the chain, using sdi of the first device as the data input. when the data transfer is complete, cs /ld is taken high, completing the instruction sequence for all devices simultaneously. a single device can be controlled by using the no-operation command (1111) for the other devices in the chain. power-down mode for power-constrained applications, power-down mode can be used to reduce the supply current whenever less than eight dac outputs are needed. when in power down, the buffer amplifiers, bias circuits and integrated reference circuits are disabled and draw essentially zero current. the dac outputs are put into a high impedance state, and the output pins are passively pulled to ground through individual 80k resistors. input- and dac-register contents are not disturbed during power down. any channel or combination of dac channels can be put into power-down mode by using command 0100b in combination with the appropriate dac address, (n). the integrated reference is automatically powered down when external reference is selected using command 0111b. in addition, all the dac channels and the integrated refer - ence together can be put into power-down mode using power-down chip command 0101b. for all power-down commands the 16-bit data word is ignored. normal operation resumes by executing any command which includes a dac update, in software as shown in table 1 or by taking the asynchronous ldac pin low. the selected dac is powered up as its voltage output is up - dated. when a dac which is in a powered-down state is powered up and updated, normal settling is delayed. if less than eight dacs are in a powered-down state prior to the update command, the power-up delay time is 12s. if, on the other hand, all eight dacs and the integrated reference
ltc2656 20 2656fa operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x cs/ld sck sdi command word address word data word don?t care c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 x x x x x x x x sdo current 32-bit input word 2656 f02b previous 32-bit input word t 2 t 3 t 4 t 1 t 8 d15 17 sck sdi sdo previous d14 previous d15 18 d14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 cs/ld sck sdi command word address word data word 24-bit input word 2656 f02a figure 2a. ltc2656-16 24-bit load sequence (minimum input word) ltc2656-12 sdi data word: 12-bit input code + 4 dont-care bits figure 2b. ltc2656-16 32-bit load sequence ltc2656-12 sdi/sdo data word: 12-bit input code + 4 dont-care bits
ltc2656 21 2656fa operation are powered down, then the main bias generation circuit bloc k has been automatically shut down in addition to the individual dac amplifiers and integrated reference. in this case, the power-up delay time is 14s. the power up of the integrated reference depends on the command that powered it down. if the reference is powered down using the select external reference command (0111b), then it can only be powered back up using select internal reference command (0110b). however if the reference was powered down using power-down chip command (0101b), then in addition to select internal reference command (0110b), any command that powers up the dacs will also power up the integrated reference. asynchronous dac update using ldac in addition to the update commands shown in table 1, the ldac pin asynchronously updates all the dac registers with the contents of the input registers. if cs /ld is high, a low on the ldac pin causes all the dac registers to be updated with the contents of the input registers. if cs /ld is low, a low going pulse on the ldac pin before the rising edge of cs /ld powers up all the dac outputs but does not cause the output to be updated. if ldac remains low after the rising edge of cs /ld, then ldac is recognized, the command specified in the 24-bit word just transferred is executed and the dac outputs are updated. the dac outputs are powered up when ldac is taken low, independent of the state of cs /ld. the integrated reference is also powered up if it was powered down us - ing power-down chip (0101b) command. the integrated reference will not power up when ldac is taken low, if it was powered down using select external reference (0111b) command. if ldac is low at the time cs /ld goes high, it inhibits any software power-down command (power down n, power- down chip, select external reference) that was specified in the input word. reference modes for applications where an accurate external reference is not available, the ltc2656 has a user-selectable, integrated reference. the ltc2656-l has a 1.25v reference that pro - vides a full-scale dac output of 2.5v. the ltc2656-h has a 2.048v reference that provides a full-scale dac output of 4.096v. both references exhibit a typical temperature drift of 2ppm/c. internal reference mode can be selected by using command 0110b, and is the power-on default. a buffer is needed if the internal reference is required to drive external circuitry. for reference stability and low noise, it is recommended that a 0.1f capacitor be tied between refcomp and gnd. in this configuration, the internal reference can drive up to 0.1f capacitive load without any stability problems. in order to ensure stable operation, the capacitive load on the refin/out pin should not exceed the capacitive load on the refcomp pin. the dac can also operate in external reference mode us - ing command 0111b. in this mode, the refin/out pin acts as an input that sets the dacs reference voltage. the input is high impedance and does not load the external reference source. the acceptable voltage range at this pin is 0.5v refin/out v cc /2. the resulting full-scale output voltage is 2 ? v refin/out . for using external refer - ence at start-up, see the power supply sequencing and start-up section. integrated reference buffers each of the eight dacs in ltc2656 has its own integrated high performance reference buffer. the buffers have very high input impedance and do not load the reference voltage source. these buffers shield the reference voltage from glitches caused by dac switching and thus minimize dac- to-dac dynamic crosstalk. typically dac-to-dac crosstalk is less than 3nv?s. by tying 0.1f capacitors between refcomp and gnd, and also between refin/out and gnd, this number can be reduced to less than 1nv?s. see the curve dac-to-dac dynamic crosstalk in the typical performance characteristics section. voltage outputs each of the ltc2656s eight rail-to-rail output amplifiers con - tained in these parts has a guaranteed load regulation when sourcing or sinking up to 15ma at 5v (7.5ma at 3v). load regulation is a measure of the amplifiers ability to maintain the rated voltage accuracy over a wide range of
ltc2656 22 2656fa load conditions. the measured change in output voltage per milliampere of forced load current change is expressed in lsb/ma. dc output impedance is equivalent to load regulation, and may be derived from it by simply calculating a change in units from lsb/ma to ohms. the amplifiers dc output impedance is 0.04 when driving a load well away from the rails. when drawing a load current from either rail, the output voltage headroom with respect to that rail is limited by the 30 typical channel resistance of the output devices; e.g., when sinking 1ma, the minimum output voltage = 30 ? 1ma = 30mv. see the graph headroom at rails vs output current in the typical performance characteristics section. the amplifiers are stable driving capacitive loads of up to 1000pf. board layout the excellent load regulation and dc crosstalk performance of these devices is achieved in part by keeping signal and power grounds separate. the pc board should have separate areas for the analog and digital sections of the circuit. this keeps digital signals away from sensitive analog signals and facilitates the use of separate digital and analog ground planes which have mini - mal capacitive and resistive interaction with each other. digital and analog ground planes should be joined at only o ne point, establishing a system star ground as close to the devices ground pin as possible. ideally, the analog ground plane should be located on the component side of the board, and should be allowed to run under the part to shield it from noise. analog ground should be a continuous and uninterrupted plane, except for necessary lead pads and vias, with signal traces on another layer. the gnd pin functions as a return path for power supply currents in the device and should be connected to analog ground. the reflo pin should be connected to the system star ground. resistance from the reflo pin to the system star ground should be as low as possible. rail-to-rail output considerations in any rail-to-rail voltage output device, the output is limited to voltages within the supply range. since the analog outputs of the device cannot go below ground, they may limit the lowest codes as shown in fig - ure 3b. similarly, limiting can occur in external reference mode near full-scale when the refin/out pin is at v cc /2. if v refin/out = v cc /2 and the dac full-scale error (fse) is positive, the output for the highest codes limits at v cc are shown in figure 3c. no full-scale limiting can occur if v refin/out (v cc C fse)/2. offset and linearity are defined and tested over the region of the dac transfer function where no output limiting can occur. operation 2656 f03 input code (3b) output voltage negative offset 0v 32,768 0 65,535 input code output voltage (3a) v ref = v cc v ref = v cc (3c) input code output voltage positive fse figure 3. effects of rail-to-rail operation on a dac transfer curve. (3a) overall transfer function (3b) effect of negative offset for codes near zero-scale (3c) effect of positive full-scale error for codes near full-scale
ltc2656 23 2656fa package description fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663) exposed pad variation cb fe20 (cb) tssop 0204 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 14 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 19 18 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc
ltc2656 24 2656fa package description ufd package 20-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1711 rev b) 4.00 0.10 (2 sides) 1.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 19 20 1 2 bottom view?exposed pad 2.50 ref 0.75 0.05 r = 0.115 typ pin 1 notch r = 0.20 or c = 0.35 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd20) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 2.65 0.05 2.50 ref 4.10 0.05 5.50 0.05 1.50 ref 3.10 0.05 4.50 0.05 package outline r = 0.05 typ 2.65 0.10 3.65 0.10 3.65 0.05 0.50 bsc
ltc2656 25 2656fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 11/10 added c-grade to data sheet 3 to 6, 9 updated electrical characteristics table for h-grade 7
ltc2656 26 2656fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2009 lt 1110 rev a ? printed in usa related parts part number description comments ltc1660/ltc1665 octal 10-/8-bit v out dacs in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1664 quad 10-bit v out dac in 16-pin narrow ssop v cc = 2.7v to 5.5v, micropower, rail-to-rail output ltc1821 single 16-bit v out dac with 1lsb inl, dnl parallel interface, precision 16-bit settling in 2s for 10v step ltc2600/ltc2610/ ltc2620 octal 16-/14-/12-bit v out dacs in 16-lead narrow ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2601/ltc2611/ ltc2621 single 16-/14-/12-bit v out dacs in 10-lead dfn 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2602/ltc2612/ ltc2622 dual 16-/14-/12-bit v out dacs in 8-lead msop 300a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2604/ltc2614/ ltc2624 quad 16-/14-/12-bit v out dacs in 16-lead ssop 250a per dac, 2.5v to 5.5v supply range, rail-to-rail output, spi serial interface ltc2605/ltc2615/ ltc2625 octal 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output ltc2606/ltc2616/ ltc2626 single 16-/14-/12-bit v out dacs with i 2 c interface 270a per dac, 2.7v to 5.5v supply range, rail-to-rail output ltc2609/ltc2619/ ltc2629 quad 16-/14-/12-bit v out dacs with i 2 c interface 250a per dac, 2.7v to 5.5v supply range, rail-to-rail output with separate v ref pins for each dac ltc2636 octal 12-/10-/8-bit v out dacs with 10ppm/c reference 125a per dac, 2.7v to 5.5v supply range, internal 1.25v or 2.048v reference, rail-to-rail output, spi interface ltc2641/ltc2642 single 16-/14-/12-bit v out dacs with 1lsb inl, dnl 1lsb (max) inl, dnl, 3mm 3mm dfn and msop packages, 120a supply current, spi interface ltc2704 quad 16-/14-/12-bit v out dacs with 2lsb inl, 1lsb dnl software programmable output ranges up to 10v, spi interface ltc2755 quad 16-/14-/12-bit i out dacs with 1lsb inl, 1lsb dnl software programmable output ranges up to 10v, parallel interface typical application + ? lt3080 in v in 1.2v to 36v v outa v outb v outc v outd v oute v outf v outg v outh 7 8 10 9 20 1 3 4 13 14 15 16 cs sck sdo sdi v control *pin numbers indicated are for the qfn package out 2656 ta02 set note: lt3080 minimum load current is 0.5ma 1 f refcomp refin/out c1 0.1f to microcontroller gnd 21 19 18 gnd reflo porsel ltc2656* v cc ldac clr 2.2f v out c1 0.1f 3 v cc jp2 v cc 1 4 2 mid-scale zero-scale c1 0.1f r4 7.5k digitally controlled output voltage 1.1a supply

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